`timescale 1ns / 1ps

`include "defines.v"
module uart_rx_tb ();

    reg clk_50m;
    reg rst_n;
    reg rx;
    wire [7:0]  data;
    wire done;

    initial begin
        $dumpfile("output/uart_rx_tb.vcd");
        $dumpvars(0, uart_rx_tb);
    end
    
    initial begin
        clk_50m = 0;
        rst_n =0;
        rx=1;
        # 100
        rst_n =1;
        #100 rx = 0 ;			//开始位
        #(5208*20) rx = 0;		//发送1011_011【0】
        #(5208*20) rx = 1;		//发送1011_01【1】0
        #(5208*20) rx = 1;		//发送1011_0【1】10
        #(5208*20) rx = 0;		//发送1011_【0】110
        #(5208*20) rx = 1;		//发送101【1】_0110
        #(5208*20) rx = 1;		//发送10【1】1_0110
        #(5208*20) rx = 0;		//发送1【0】11_0110
        #(5208*20) rx = 1;		//发送【1】011_0110
        #(5208*20) rx = 1;		//发送停止位
        
        #(5208*20) rx = 0;		//开始位
        #(5208*20) rx = 1;		
        #(5208*20) rx = 0;		
        #(5208*20) rx = 0;		
        #(5208*20) rx = 0;		
        #(5208*20) rx = 1;		
        #(5208*20) rx = 0;		
        #(5208*20) rx = 1;		
        #(5208*20) rx = 1;		
        #(5208*20) rx = 1;		//发送停止位

        #(5208*20) $stop;
    end

    always #10 clk_50m = ~clk_50m;
    
    uart_rx inst_rx(
        .clk_50m		(clk_50m),
        .rst_n			(rst_n),
        .rx				(rx),
        .q			    (data),
        .done			(done)
    );

endmodule  //uart_rx_tb